1. Field of the Invention
The present invention generally pertains to semiconductor wafer fabrication and, in particular, methods and apparatus for predicting fabrication process variations.
2. Related Art
Successful IC (integrated circuit) development results in an IC, or “chip”, that reaches mass production in a semiconductor manufacturing factory often referred to as a “fab”. ICs are the building blocks of modern day electronics ranging from consumer, commercial, industrial, and aerospace and defense applications. In order to reach production from IC conception, an IC designer follows a sequence of design steps performed in a computer aided design or CAD environment through specialized software referred to as a process design kit or PDK. The IC is then physically fabricated following a predefined set of fab manufacturing recipes, construction flows, and process conditions. The fabricated IC is then measured and tested in an electronics laboratory for accuracy and robustness to the design specifications. If the IC does not meet design specifications, the IC typically enters a re-design phase and the fabrication process is repeated. If the fabricated IC meets design specifications, the product qualification phase is entered. In general, product qualification is the process of demonstrating that an entity is capable of meeting or exceeding the specified requirements, including, without limitation, performance characteristic, quality, reliability, or environmental requirements.
A significant component of product qualification is investigation of IC functionality, and robustness to design specifications, over semiconductor process variation. Variations in semiconductor manufacturing process technology are unavoidable due to variations in manufacturing equipment and environment control tolerances. Process variation can be manifested in variations of both device and interconnect electrical performance. As ICs are composed of various devices electrically wired together through interconnect, the IC designers must ensure the IC will operate and yield to design specifications at the extremes of semiconductor process variation. To achieve this end, the IC is fabricated through Split Lots also referred to as “Corner Lots,” which introduce specific process variations through semiconductor process recipe changes. The motivation for Split Lots is to provide the IC designer with IC performance characteristic metrics across process variation extremes without having to mass fabricate a large amount of wafers over an extended time period to obtain the process variation from statistics in a manual fashion.
A split lot is typically composed of plural split condition wafers. A Split Condition is a fabrication process recipe that produces the desired process parameter perturbations. A Split Condition wafer is created by perturbing the physical process parameters through fabrication recipe changes. There may be hundreds (or more) of physical process parameters from which the conditions for a given split lot may be selected. IC designers are forced to choose which Split Conditions are expected to incur the most sensitivity of the IC performance characteristic to design specifications. Once the Split Conditions are chosen, silicon wafers containing the IC are fabricated for each Split Condition. As each Split Condition typically corresponds to minimum of 2 fabricated silicon wafers, the number of Split Conditions fabricated into wafers is limited in practice. A typical Split Lot will be formed by grouping 24-48 wafers corresponding from 12-24 Split Condition wafers. After fabrication, IC devices from the Split Lot are measured and tested for robustness and yield, in accordance with IC design specifications.
Each split and, indeed, a split lot, may provide a wealth of data pertaining to correlations between parametric value perturbations and product yields. In practice, the effectiveness of the Split Conditions is based on the expertise level of the IC designer and related experience with the particular IC design applications and subsequent sensitivities to process variation. During split lot fabrication, unintended variations in, for example, temperatures, pressures, doping or metal distribution, may accompany an intended device parameter perturbation. If the process parameters that are perturbed generate inconclusive, confounding, or uninformative data, an additional split lot run may be required, this time using different perturbed parameters or re-evaluating prior parameter perturbations. Given that many Split Conditions are not actually fabricated and investigated for IC compliance to design specifications, the Split Lot process is often rendered an incomplete and inadequate method to ensure IC compliance to process variation. Furthermore, the Split Lot process is a costly in terms of time and money spent on engineering resources and wafer fabrication. The additional time to complete the Split Lot process ultimately delays production ramp which can lead to loss of market opportunity.